1. Field of the Invention
This invention relates to the Complementary Junction Field Effect Transistors (CJFETs) that can be used in high speed electronic circuits for low voltage and/or large current applications. This invention is using enhancement mode or normally "off" Junction Field Effect Transistors with an N-channel JFET and a P-channel JFET in series connection. The gates of both normally "off" JFETs are connected together. This forms the Complementary Junction Field Effect Transistors.
2. Description of the Prior Art
The concept of Junction Field Effect Transistor (JFET) is well known since the invention of the junction transistors. Junction Field Effect Transistor is a majority carrier device, it offers high frequency response. However, the normally "off" JFET is using a P-N junction as the gate so that it is effective to turn-off the device by reverse bias the gate. This normally "on" or depletion mode FET is available in the market. Without readily available normally "off" or enhancement mode version, JFETs are not widely used as the MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). In order to make the normally "off" FET, the distance between the gates must be smaller enough so that the depletion regions from both gates fill up the conduction channel. No current is flow when the gate is at zero bias. This means that at forward bias above the threshold voltage, the depletion region is smaller enough, the conduction channels between source and drain are open.
S. M. Sze has clearly described this concept in page 323, "Physics of Semiconductor Devices", 2.sup.nd edition, John Wiley & Son, 1981. The symbols for N-type and P-type normally "on" and normally "off" JFET and MESFET are illustrated. However, in this book, the application of normally "off" JFET is described for high speed and low power application. Since the original device structure has very long channel length that limits the current carrying capability and high on resistance.
This inventor, Ho-Yuan Yu, has filed the following inventions: 1) "Low On Resistance Transistors and the Method of Making", filed in Patent Office of Disclosed Document Program, Sep. 24, 1998, #444899, has disclosed the device structures for high current and low on resistance applications. This is a normally "on" JFET. 2) "Novel Structure of JFETs for Low Voltage Application", filed in Patent Office of Disclosed Document Program, Sep. 17, 1998, #444874, disclosed the device structures of normally "off" JFETs for low voltage and high current applications. Above two documents have combined together to file a provisional patent application, #60/115,009 on Jan. 6, 1999 and filed utility patent application on Oct. 28, 1999. Present invention is using normally "off" JFETs with the structures shown in #60/115,009 and additional structures shown in this patent application with both N-channel and P-channel JFETs to perform the complementary circuitry function that can be used in high speed, low voltage and high current applications.